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clocked flip-flop
释义
clocked flip-flop
clocked flip-flop
[
′kläkt ′flip‚fläp
]
(electronics)
A flip-flop circuit that is set and reset at specific times by adding clock pulses to the input so that the circuit is triggered only if both trigger and clock pulses are present simultaneously.
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更新时间:2026/11/6 14:05:07