bus master

(architecture)The device in a computer which is driving theaddress bus and bus control signals at some point in time.In a simple architecture only the (single) CPU can be busmaster but this means that all communications between("slave") I/O devices must involve the CPU. Moresophisticated architectures allow other capable devices (ormultiple CPUs) to take turns at controling the bus. Thisallows, for example, a network controller card to access adisk controller directly while the CPU performs other taskswhich do not require the bus, e.g. fetching code from itscache.

Note that any device can drive data onto the data bus whenthe CPU reads from that device, but only the bus master drivesthe address bus and control signals.

Direct Memory Access is a simple form of bus mastering wherethe I/O device is set up by the CPU to read from or write toone or more contiguous blocks of memory and then signal to theCPU when it has done so. Full bus mastering (or "First PartyDMA", "bus mastering DMA") implies that the I/O device iscapable of performing more complex sequences of operationswithout CPU intervention (e.g. servicing a complete NFSrequest). This will normally mean that the I/O devicecontains its own processor or microcontroller.

See also distributed kernel.

单词	bus master
释义	bus master bus master (architecture)The device in a computer which is driving theaddress bus and bus control signals at some point in time.In a simple architecture only the (single) CPU can be busmaster but this means that all communications between("slave") I/O devices must involve the CPU. Moresophisticated architectures allow other capable devices (ormultiple CPUs) to take turns at controling the bus. Thisallows, for example, a network controller card to access adisk controller directly while the CPU performs other taskswhich do not require the bus, e.g. fetching code from itscache. Note that any device can drive data onto the data bus whenthe CPU reads from that device, but only the bus master drivesthe address bus and control signals. Direct Memory Access is a simple form of bus mastering wherethe I/O device is set up by the CPU to read from or write toone or more contiguous blocks of memory and then signal to theCPU when it has done so. Full bus mastering (or "First PartyDMA", "bus mastering DMA") implies that the I/O device iscapable of performing more complex sequences of operationswithout CPU intervention (e.g. servicing a complete NFSrequest). This will normally mean that the I/O devicecontains its own processor or microcontroller. See also distributed kernel.
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