scan register
scan register
The most common design is a multiplexed flip-flop:
___ ____normal in --| \\ | || |------|D Q|---- normal/scan outputscan in ----|___/ mux | || | |test mode ----+ +----|> | flip-flop| |____|clk ---------------+
The addition of a multiplexor (mux) to each flip-flop'sinput allows operation in either normal or test mode. Theoutput of each flip-flop goes to the normal functional logicas well as to the scan input of the next multiplexor in thescan path.
The other common design is level-sensitive scan design(LSSD).