pipeline burst cache


Pipeline Burst Cache

(hardware, storage)(PB Cache) A synchronous cache builtfrom pipelined SRAM.

A cache in which reading or writing a new location takesmultiple cycles but subsequent locations can be accessed ina single cycle. On Pentium systems in 1996, pipeline burstcaches are frequently used as secondary caches. The first 8bytes of data are transferred in 3 CPU cycles, and thenext 3 8-byte pieces of data are transferred in one cycleeach.

pipeline burst cache

A common type of static RAM chip used for memory caches. After the first byte is accessed, access to subsequent memory locations takes fewer machine cycles than with previous designs. See L2 cache and static RAM.