Microprocessor without Interlocked Pipeline Stages

(processor)(MIPS) A project at Stanford University intendedto simplify processor design by eliminating hardwareinterlocks between the five pipeline stages. This meansthat only single execution cycle instructions can access thethirty two 32-bit general registers, so that the compilercan schedule them to avoid conflicts. This also means thatLOAD/STORE and branch instructions have a one-cycle delay toaccount for. However, because of the importance of multiplyand divide instructions, a special HI/LO pair ofmultiply/divide registers exist which do have hardwareinterlocks, since these take several cycles to execute andcomplicate instruction scheduling.

The project eventually lead to the commercial MIPS R2000processor.

单词	microprocessor without interlocked pipeline stages
释义	Microprocessor without Interlocked Pipeline Stages Microprocessor without Interlocked Pipeline Stages (processor)(MIPS) A project at Stanford University intendedto simplify processor design by eliminating hardwareinterlocks between the five pipeline stages. This meansthat only single execution cycle instructions can access thethirty two 32-bit general registers, so that the compilercan schedule them to avoid conflicts. This also means thatLOAD/STORE and branch instructions have a one-cycle delay toaccount for. However, because of the importance of multiplyand divide instructions, a special HI/LO pair ofmultiply/divide registers exist which do have hardwareinterlocks, since these take several cycles to execute andcomplicate instruction scheduling. The project eventually lead to the commercial MIPS R2000processor. AcronymsSeeMIPS
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