machine cycle

[mə′shēn ‚sī·kəl] (computer science) The shortest period of time at the end of which a series of events in the operation of a computer is repeated. The series of events itself.

machine cycle

(processor)The four steps which the CPU carries out foreach machine language instruction: fetch, decode, execute,and store. These steps are performed by the control unit,and may be fixed in the logic of the CPU or may be programmedas microcode which is itself usually fixed (in ROM) butmay be (partially) modifiable (stored in RAM).

The fetch cycle places the current program counter contents(the address of the next instruction to execute) on theaddress bus and reads in the word at that location into theinstruction register (IR). In RISC CPUs instructions areusually a single word but in other architectures aninstruction may be several words long, necessitating severalfetches.

The decode cycle uses the contents of the IR to determinewhich gates should be opened between the CPU's variousfunctional units and busses and what operation the ALU(s)should perform (e.g. add, bitwise and). Each gate allowsdata to flow from one unit to another (e.g. from register 0to ALU input 1) or enables data from one output onto a certainbus. In the simplest case ("horizontal encoding") eachbit of the instruction register controls a single gate orseveral bits may control the ALU operation. This is rarelyused because it requires long instruction words (such anarchitecture is sometimes called a very long instruction word architecture). Commonly, groups of bits from the IR arefed through decoders to control higher level aspects of theCPU's operation, e.g. source and destination registers,addressing mode and ALU operation. This is known asvertical encoding. One way RISC processors gain theiradvantage in speed is by having simple instruction decodingwhich can be performed quickly.

The execute cycle occurs when the decoding logic has settledand entails the passing of values between the various functionunits and busses and the operation of the ALU. A simpleinstruction will require only a single execute cycle whereas acomplex instruction (e.g. subroutine call or one using memoryindirect addressing) may require three or four.Instructions in a RISC typically (but not invariably) takeonly a single cycle.

The store cycle is when the result of the instruction iswritten to its destination, either a register or a memorylocation. This is really part of the execute cycle becausesome instructions may write to multiple destinations as partof their execution.

machine cycle

The shortest interval in which an elementary operation can take place within the processor. It is made up of some number of clock cycles.

单词	machine cycle
释义	DictionarySeecycle machine cycle machine cycle [mə′shēn ‚sī·kəl] (computer science) The shortest period of time at the end of which a series of events in the operation of a computer is repeated. The series of events itself. machine cycle (processor)The four steps which the CPU carries out foreach machine language instruction: fetch, decode, execute,and store. These steps are performed by the control unit,and may be fixed in the logic of the CPU or may be programmedas microcode which is itself usually fixed (in ROM) butmay be (partially) modifiable (stored in RAM). The fetch cycle places the current program counter contents(the address of the next instruction to execute) on theaddress bus and reads in the word at that location into theinstruction register (IR). In RISC CPUs instructions areusually a single word but in other architectures aninstruction may be several words long, necessitating severalfetches. The decode cycle uses the contents of the IR to determinewhich gates should be opened between the CPU's variousfunctional units and busses and what operation the ALU(s)should perform (e.g. add, bitwise and). Each gate allowsdata to flow from one unit to another (e.g. from register 0to ALU input 1) or enables data from one output onto a certainbus. In the simplest case ("horizontal encoding") eachbit of the instruction register controls a single gate orseveral bits may control the ALU operation. This is rarelyused because it requires long instruction words (such anarchitecture is sometimes called a very long instruction word architecture). Commonly, groups of bits from the IR arefed through decoders to control higher level aspects of theCPU's operation, e.g. source and destination registers,addressing mode and ALU operation. This is known asvertical encoding. One way RISC processors gain theiradvantage in speed is by having simple instruction decodingwhich can be performed quickly. The execute cycle occurs when the decoding logic has settledand entails the passing of values between the various functionunits and busses and the operation of the ALU. A simpleinstruction will require only a single execute cycle whereas acomplex instruction (e.g. subroutine call or one using memoryindirect addressing) may require three or four.Instructions in a RISC typically (but not invariably) takeonly a single cycle. The store cycle is when the result of the instruction iswritten to its destination, either a register or a memorylocation. This is really part of the execute cycle becausesome instructions may write to multiple destinations as partof their execution. machine cycle The shortest interval in which an elementary operation can take place within the processor. It is made up of some number of clock cycles. FinancialSeeCycleSee MCY See MCY
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