MIPS R2000

MIPS R2000

(processor)The R2000 design came, in about 1987, from theStanford MIPS project, which stood for Microprocessorwithout Interlocked Pipeline Stages.

Like the AMD 29000, the R2000 has no condition code register considering it a potential bottleneck. Theprogram counter can be read like other registers.

The CPU includes an MMU that can also control a cache, andthe CPU can operate as big-endian or little-endian. Thereis a FPU, the R2010.

Versions include the MIPS R3000 and MIPS R4000.