Joint Test Action Group


Joint Test Action Group

(architecture, body, electronics, integrated circuit,standards, testing)(JTAG, or "IEEE Standard 1149.1") Astandard specifying how to control and monitor the pins ofcompliant devices on a printed circuit board.

Each device has four JTAG control lines. There is a commonreset (TRST) and clock (TCLK). The data line daisy chainsone device's TDO pin to the TDI pin on the next device.

The protocol contains commands to read and set the values ofthe pins (and, optionally internal registers) of devices.This is called "boundary scanning". The protocol makesboard testing easier as signals that are not visible at theboard connector may be read and set.

The protocol also allows the testing of equipment, connectedto the JTAG port, to identify components on the board (byreading the device identification register) and to control andmonitor the device's outputs.

JTAG is not used during normal operation of a board.

JTAG Technologies B.V..

Boundary Scan/JTAG Technical Information - Xilinx, Inc..

Java API for Boundary Scan FAQs - Xilinx Inc..

JTAG Boundary-Scan Test Products - Corelis, Inc..

"Logic analyzers stamping out bugs at the cutting edge", EDN Access, 1997-04-10.

IEEE 1149.1 Device Architecture - Boundary-Scan Tutorial from ASSET InterTech, Inc..

"Application-Specific Integrated Circuits", Michael John Sebatian Smith, published Addison-Wesley - Design Automation Cafe.

Software Debug options on ASIC cores - Embedded Systems Programming Archive.

Designing for On-Board Programming Using the IEEE 1149.1.

Built-In Self-Test Using Boundary Scan by Texas Instruments - EDTN Network.