Intersil 6100

(programming)(IMS 6100) A single chip design of the DECPDP-8 minicomputer. The old PDP-8 design was verystrange, and if it hadn't been popular, an awkward CPU likethe 6100 would never been designed.

The 6100 was a 12-bit processor, which had three registers:the PC, AC (accumulator), and MQ. All 2-operandinstructions read AC and MQ and wrote back to AC. It had a12-bit address bus, limiting RAM to only 4K. Memoryreferences were 7-bit, offset either from address 0, or fromthe PC page base address (PC AND 7600 oct).

It had no stack. Subroutines stored the PC in the firstword of the subroutine code itself, so recursion requiredfancy programming.

4K RAM was pretty much hopeless for general purpose use. The6102 support chip (included in the 6120) added 3 addresslines, expanding memory to 32K the same way that the PDP-8/Eexpanded the PDP-8. Two registers, IFR and DFR, held the pagefor instructions and data respectively (IFR was always useduntil a data address was detected). At the top of the 4Kpage, the PC wrapped back to 0, so the last instruction on apage had to load a new value into the IFR if execution was tocontinue.

单词	intersil 6100
释义	Intersil 6100 Intersil 6100 (programming)(IMS 6100) A single chip design of the DECPDP-8 minicomputer. The old PDP-8 design was verystrange, and if it hadn't been popular, an awkward CPU likethe 6100 would never been designed. The 6100 was a 12-bit processor, which had three registers:the PC, AC (accumulator), and MQ. All 2-operandinstructions read AC and MQ and wrote back to AC. It had a12-bit address bus, limiting RAM to only 4K. Memoryreferences were 7-bit, offset either from address 0, or fromthe PC page base address (PC AND 7600 oct). It had no stack. Subroutines stored the PC in the firstword of the subroutine code itself, so recursion requiredfancy programming. 4K RAM was pretty much hopeless for general purpose use. The6102 support chip (included in the 6120) added 3 addresslines, expanding memory to 32K the same way that the PDP-8/Eexpanded the PDP-8. Two registers, IFR and DFR, held the pagefor instructions and data respectively (IFR was always useduntil a data address was detected). At the top of the 4Kpage, the PC wrapped back to 0, so the last instruction on apage had to load a new value into the IFR if execution was tocontinue.
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